Pin Descriptions Grouped by Function
53
TLU SRAM Interface The TLU SRAM interface supports up to 128MBytes of SRAM at frequencies to 125MHz
Signals
using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to
64Mbits. The TLU SRAM interface signals are described in Table 23.
Table 23 TLU SRAM Interface Signals
SIGNAL NAME
PIN #
TOTAL TYPE
I/O
SIGNAL DESCRIPTION
TD0 - TD63
F3, F4, F5, F6, F7, F8, G1, G3, G4, G5, G7, G8, H1, H2, 64
H3, H5, H6, H7, H8, J1, J2, J3, J5, J6, J7, J8, K1, K3,
K4, K5, K7, K8, L1, L2, L3, L4, L5, L6, L7, L8, M1, M2,
M3, M5, M6, M7, M8, N1, N2, N3, N4, N5, N6, N7,
N8, P1, P3, P4, P5, P7, P8, R1, R2, R3
LVTTL IPD/O TLU Memory Data
TA0 - TA21
U2, U3, U4, U5, U6, U7, U8, V1, V3, V4, V5, V7, V8, 22
W1, W2, W3, W5, W6, W7, W8, Y1, Y2
LVTTL OPD TLU Memory Address
TPAR0 - TPAR3
T1, T2, T3, T5
4
LVTTL IPD/O Word Data Parity (i.e. TPAR0 across
TD15:0)
TCE0X - TCE3X
TWE0X - TWE3X
TCLKI
T6, T7, T8, U1
R5, R6, R7, R8
R4
4
LVTTL OPD TLU Memory Chip Enable
LVTTL OPD TLU Memory Write Enable
4
1
LVTTL IPD
TLU Clock Input
99
TOTAL PINS
03
FREESCALE [ Freescale ]
