52
CHAPTER 2: SIGNAL DESCRIPTIONS
Table 22 BMU SDRAM Interface Signals (continued)
SIGNAL NAME
PIN #
TOTAL TYPE
I/O
SIGNAL DESCRIPTION
MRASX
A23
1
1
1
LVTTL
LVTTL
LVTTL
OPD Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX
is considered part of the command code.
MWEX
MCSX
A22
A25
OPD Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX
is considered part of the command code.
OPD Chip Select: MCSX enables (registered LOW) and
disables (registered HIGH) the command decoder.
All commands are masked when MCSX is
registered HIGH. MCSX provides the external bank
selection on systems with multiple banks. MCSX is
considered part of the command code.
MDQM
MDQML
A20
A21
1
1
LVTTL
LVTTL
OPD Input/Output Mask: MDQM is an input mask
signal for write accesses and an output enable
OPD
signal for read accesses. Input data is masked
when MDQM is sampled HIGH during a WRITE
cycle. The output buffers are placed in a high Z
state (two-clock latency) when MDQM is sampled
HIGH during the READ cycle.
NOTE: MDQML is an identical copy of MDQM
used to drive the loading on SDRAM
configurations with 2 DQM pins.
MDCLK
A26
1
LVTTL
IPD
Clock: MDCLK is driven by the system clock. All
SDRAM input signals are sampled on the positive
edge of the MDCLK. MDCLK also increments the
internal burst counter and controls the output
registers.
160
TOTAL PINS
C3EN
FREESCALE [ Freescale ]
