Pin Descriptions Grouped by Function
57
Test Signals Test signals are described in Table 27.
Table 27 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines
SIGNAL NAME
JTCK
PIN #
B17
TOTAL TYPE
I/O
SIGNAL DESCRIPTION
1
1
LVTTL IPD
Test Clock
JTMS
A17
LVTTL IPD
Test Mode Select. High selects modes
as defined in the IEEE 1149.1 JTAG
specification.
JTRSTX
JTDI
A16
C16
C14
B15
A15
1
1
1
1
1
LVTTL IPD
LVTTL IPD
Test Reset (low active)
Test Data In
JTDO
LVTTL
O
Test Data Out
JHIGHZ
JCLKBYP
LVTTL IPD
LVTTL IPD
Turns off all output drivers when High
1X or 2X Clock Mode Select. Low
selects 1X, High selects 2X.
JSE
D15
1
LVTTL IPD
Scan Enable. High enables scan test.
Scan Out Pins
JS00-JS05
TOTAL PINS
C13, B13, A13, B14, A14, C15
6
LVTTL
O
14
During JTAG, SCLK and SCLKX must remain as differential inputs.
03
FREESCALE [ Freescale ]
