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CHAPTER 2: SIGNAL DESCRIPTIONS
QMU SRAM (Internal The QMU signals are described in Table 24.
Mode) Interface Signals
Table 24 QMU SRAM (Internal Mode) Interface Signals
SIGNAL NAME
PIN #
TOTAL TYPE
LVTTL
I/O
SIGNAL DESCRIPTION
QA0 - QA16
D10, C10, A10, F11, E11, D11, C11, B11, A11, F12, 17
E12, D12, C12, A12, F13, E13, D13
O
Address [16:0]
QD0 - QD31
F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3, B3, A3, 32
D4, B4, A4, E5, D5, C5, B5, A5, E6, C6, A6, E7, D7,
C7, B7, A7, E8, D8
LVTTL IPD/O Data
QDQPAR
QARDY
QNQRDY
QWEX
C8
F10
A9
E10
B8
1
LVTTL IPD
LVTTL IPD
LVTTL IPD
nc
1
nc
1
nc
1
LVTTL
LVTTL
O
O
Write Enable
QBCLKO
QBCLKI
QACLKO
QACLKI
QDPL
1
nc
A8
F9
1
LVTTL IPD
LVTTL
LVTTL IPD
nc
1
O
nc
E9
1
Input Clock
C9
B9
1
LVTTL IPD/O Data Parity Low
LVTTL IPD/O Data Parity High
QDPH
1
59
TOTAL PINS
C3EN
FREESCALE [ Freescale ]
