欢迎访问ic37.com |
会员登录 免费注册
发布采购

AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
 浏览型号AN1063D的Datasheet PDF文件第383页浏览型号AN1063D的Datasheet PDF文件第384页浏览型号AN1063D的Datasheet PDF文件第385页浏览型号AN1063D的Datasheet PDF文件第386页浏览型号AN1063D的Datasheet PDF文件第388页浏览型号AN1063D的Datasheet PDF文件第389页浏览型号AN1063D的Datasheet PDF文件第390页浏览型号AN1063D的Datasheet PDF文件第391页  
Freescale Semiconductor, Inc.  
The MC68340 includes on-chip circuitry to detect the initial application of power to the  
device. Power-on reset (POR), the output of this circuitry, is used to reset both the system  
and IEEE 1149.1 logic. The purpose for applying POR to the IEEE 1149.1 circuitry is to  
avoid the possibility of bus contention during power-on. The time required to complete  
device power-on is power-supply dependent. However, the IEEE 1149.1 TAP controller  
remains in the test-logic-reset state while POR is asserted. The TAP controller does not  
respond to user commands until POR is negated.  
The MC68340 features a low-power stop mode that uses a CPU instruction called  
LPSTOP. The interaction of the IEEE 1149.1 interface with LPSTOP mode is as follows:  
1. Leaving the TAP controller test-logic-reset state negates the ability to achieve  
minimal power consumption, but does not otherwise affect device functionality.  
2. The TCK input is not blocked in LPSTOP mode. To consume minimal power, the  
TCK input should be externally connected to V  
or ground.  
CC  
3. The TMS and TDI pins include on-chip pullup resistors. In LPSTOP mode, these two  
pins should remain either unconnected or connected to V to achieve minimal  
CC  
power consumption.  
9.6 NON-IEEE 1149.1 OPERATION  
In non-IEEE 1149.1 operation, there are two constraints. First, the TCK input does not  
include an internal pullup resistor and should be pulled up externally to preclude mid-level  
inputs. The second constraint is to ensure that the IEEE 1149.1 test logic is kept  
transparent to the system logic by forcing the TAP controller into the test-logic-reset state,  
using either of two methods. During power-on, POR forces the TAP controller into this  
state. Alternatively, sampling TMS as a logic one for five consecutive TCK rising edges  
also forces the TAP controller into this state. If TMS either remains unconnected or is  
connected to V  
regardless of the state of TCK.  
, then the TAP controller cannot leave the test-logic-reset state,  
CC  
9- 12  
MC68340 USER’S MANUAL  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
 复制成功!