Freescale Semiconductor, Inc.
DMA READ
S2
DMA READ
S2 S4
CPU CYCLE
S0
CPU CYCLE
S2 S4
S0
S0
S4
S0
CLKOUT
A31–A0
FC3–FC0
SIZ1–SIZ0
AS
DS
R/W
D15–D0
DSACKx
DREQx
DONEx
.
DACKx
DONEx
(OUTPUT)
NOTE:
1. Timing to generate more than one DMA request.
2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.
3. DREQx must be asserted while DACKx is asserted and meet the setup and hold times for
more than one DMA transfer to be recognized.
Figure 6-5. Single-Address Read Timing (External Burst)
6- 8
MC68340 USER’S MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
