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Therefore, if a peripheral generates it asynchronously, it must be at least two clock
periods long.
The DMA channel responds to cycle steal requests the same as all other requests.
However, if subsequent DREQ≈ pulses are generated before DACK≈ is asserted in
response to each request, they are ignored. If DREQ≈ is asserted after the DMA channel
asserts DACK≈ for the previous request but before DACK≈ is negated, then the new
request is serviced before bus ownership is released. If a new request is not generated by
the time DACK≈ is negated, the bus is released.
6.3.2.3 EXTERNAL REQUEST WITH OTHER MODULES. The DMA controller can be
externally connected to the serial module and used in conjunction with the serial module
to send or receive data. The DMA takes the place of a separate service routine for
accessing or storing data that is sent or received by the serial module. Using the DMA
also lowers the CPU32 overhead required to handle the data transferred by the serial
module. Figure 6-4 shows the external connections required for using the DMA with the
serial module.
DMA MODULE
..
SERIAL MODULE
.
DREQ1
DREQ2
TxRDYA
RxRDYA
Figure 6-4. DMA External Connections to Serial Module
For serial receive, the DMA reads data from the serial receive buffer (RB) register (when
the serial module has filled the buffer on input) and writes data to memory. For serial
transmit, the DMA reads data from memory and writes data to the serial transmit buffer
(TB) register. Only dual-address mode can be used with the serial module. The MC68340
on-chip peripherals do not support single-address transfers.
The timer modules can be used with the DMA in a similar manner. By connecting TOUTx
to DREQ≈, the timer can request a DMA transfer.
6.4 DATA TRANSFER MODES
The DMA channel supports single- and dual-address transfers. The single-address
transfer mode consists of one DMA bus cycle, which allows either a read or a write cycle
to occur. The dual-address transfer mode consists of a source operand read and a
destination operand write. Two DMA bus cycles are executed for the dual-address mode:
a DMA read cycle and a DMA write cycle.
6.4.1 Single-Address Mode
The single-address DMA bus cycle allows data to be transferred directly between a device
and memory without going through the DMA. In this mode, the operand transfer takes
6- 6
MC68340 USER’S MANUAL
MOTOROLA
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