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AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
place in one bus cycle, where only the memory is explicitly addressed. The DMA bus  
cycle may be either a read or a write cycle. The DMA provides the address and control  
signals required for the operation. The requesting device either sends or receives data to  
or from the specified address. Only external requests can be used to start a transfer when  
the single-address mode is selected. An external device uses DREQto request a  
transfer.  
Each DMA channel can be independently programmed to provide single-address  
transfers. The CCR ECO bit controls whether a source read or a destination write cycle  
occurs on the data bus. If the ECO bit is set, the external handshake signals are used with  
the source operand and a single-address source read occurs. If the ECO bit is cleared,  
the external handshake signals are used with the destination operand, and a single-  
address destination write occurs. The channel can be programmed to operate in either  
burst transfer mode or cycle steal mode. See 6.7 Register Description for more  
information.  
If external 32-bit devices and a 32-bit bus are used with the MC68340, the DMA can  
control 32-bit transfers between devices that use the 32-bit bus in single-address mode  
only. External logic is required to complete a 32-bit (long-word) transfer. If both byte and  
word devices are used on an external bus, then an external multiplexer must be used to  
correctly transfer data. The SIZx and A0 signals can be used to control this external  
multiplexer.  
6.4.1.1 SINGLE-ADDRESS READ. During the single-address source (read) cycle, the  
DMA controls the transfer of data from memory to a device. The memory selected by the  
address specified in the source address register (SAR), the source function codes in the  
function code register (FCR), and the source size in the CCR provides the data and  
control signals on the data bus. This bus cycle operates like a normal read bus cycle. The  
DMA control signals (DACKand DONE) are asserted in the source (read) cycle. See  
Figures 6-5 and 6-6 for timing diagrams single-address read for external burst and cycle  
steal modes.  
MOTOROLA  
MC68340 USER’S MANUAL  
6- 7  
For More Information On This Product,  
Go to: www.freescale.com  
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