Freescale Semiconductor, Inc.
5.1.1 Features
Features of the CPU32 are as follows:
• Fully Upward Object-Code Compatible with M68000 Family
• Virtual Memory Implementation
• Loop Mode of Instruction Execution
• Fast Multiply, Divide, and Shift Instructions
• Fast Bus Interface with Dynamic Bus Port Sizing
• Improved Exception Handling for Embedded Control Applications
• Additional Addressing Modes
— Scaled Index
— Address Register Indirect with Base Displacement and Index
— Expanded PC Relative Modes
— 32-Bit Branch Displacements
• Instruction Set Additions
— High-Precision Multiply and Divide
— Trap On Condition Codes
— Upper and Lower Bounds Checking
• Enhanced Breakpoint Instruction
• Trace on Change of Flow
• Table Lookup and Interpolate Instruction
• LPSTOP Instruction
• Hardware BKPT Signal, Background Mode
• Fully Static Implementation
A block diagram of the CPU32 is shown in Figure 5-1. The major blocks depicted operate
in a highly independent fashion that maximizes concurrences of operation while managing
the essential synchronization of instruction execution and bus operation. The bus
controller loads instructions from the data bus into the decode unit. The sequencer and
control unit provide overall chip control, managing the internal buses, registers, and
functions of the execution unit.
5.1.2 Virtual Memory
A system that supports virtual memory has a limited amount of high-speed physical
memory that can be accessed directly by the processor and maintains an image of a
much larger virtual memory on a secondary storage device. When the processor attempts
to access a location in the virtual memory map that is not resident in physical memory, a
page fault occurs. The access to that location is temporarily suspended while the
necessary data is fetched from secondary storage and placed in physical memory. The
5- 2
MC68340 USER’S MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
