Freescale Semiconductor, Inc.
Electrical Specifications
Table 19-6. Analog Converter Characteristics (Operating)
V
DD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted
Characteristic
Symbol
1 count
DNL
Min
Typical
Max
Unit
mV
8-bit resolution(1)
20
8-bit differential non-linearity(2)
−0.5
−1
+0.5
+1
count
count
count
8-bit integral non-linearity(2)
INL
8-bit absolute error,(3)2, 4, 8, and 16 ATD sample clocks
AE
−1
+1
10-bit resolution(1)
1 count
DNL
INL
5
mV
10-bit differential non-linearity(2)
10-bit integral non-linearity(2)
–2
–2
2
2
count
count
count
10-bit absolute error(3) 2, 4, 8, and 16 ATD sample clocks
AE
–2.5
2.5
See
note(4)
RS
20
Maximum source impedance
KΩ
1. VRH − VRL ≥ 5.12V; VDDA − VSSA = 5.12V
2. At VREF = 5.12V, one 8-bit count = 20 mV, and one 10-bit count = 5mV.
INL and DNL are characterized using the process window parameters affecting the ATD accuracy, but they are not tested.
3. These values include quantization error which is inherently 1/2 count for any A/D converter.
4. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into
the pin and on leakage due to charge-sharing with internal capacitance.
Error from junction leakage is a function of external source impedance and input leakage current. Expected error in result
value due to junction leakage is expressed in voltage (VERRJ):
VERRJ = RS × IOFF
where IOFF is a function of operating temperature. Charge-sharing effects with internal capacitors are a function of ATD clock
speed, the number of channels being scanned, and source impedance. Charge pump leakage is computed as follows:
VERRJ = .25pF × VDDA × RS × ATDCLK/(8 × number of channels)
Technical Data
MC68HC912DG128 — Rev 3.0
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
