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68HC912DG128PV8 参数 Datasheet PDF下载

68HC912DG128PV8图片预览
型号: 68HC912DG128PV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Development Support  
Background Debug Mode  
18.4.5.1 STATUS  
The STATUS register is read and written by the BDM hardware as a  
result of serial data shifted in on the BKGD pin.  
Read: all modes.  
Write: Bits 3 through 5, and bit 7 are writable in all modes. Bit 6,  
BDMACT, can only be written if bit 7 H/F in the INSTRUCTION register  
is a zero. Bit 2, CLKSW, can only be written if bit 7 H/F in the  
INSTRUCTION register is a one. A user would never write ones to bits  
3 through 5 because these bits are only used by BDM firmware.  
BIT 7  
6
5
4
3
2
1
-
BIT 0  
-
ENBDM  
BDMACT  
ENTAG  
SDV  
TRACE  
CLKSW  
Special  
Single Chip  
& Periph  
0
RESET:  
1
0
0
0
0
0
0
0
0
0
(NOTE 1)  
All other  
modes  
RESET:  
0
0
0
0
0
STATUS— BDM Status Register(1)  
1. ENBDM is set to 1 by the firmware in Special Single Chip mode.  
$FF01  
ENBDM — Enable BDM (permit active background debug mode)  
0 = BDM cannot be made active (hardware commands still  
allowed).  
1 = BDM can be made active to allow firmware commands.  
BDMACT — Background Mode Active Status  
BDMACT becomes set as active BDM mode is entered so that the  
BDM firmware ROM is enabled and put into the map. BDMACT is  
cleared by a carefully timed store instruction in the BDM firmware as  
part of the exit sequence to return to user code and remove the BDM  
memory from the map. This bit has 4 clock cycles write delay.  
0 = BDM is not active. BDM ROM and registers are not in map.  
1 = BDM is active and waiting for serial commands. BDM ROM and  
registers are in map  
MC68HC912DG128 — Rev 3.0  
Technical Data  
Development Support  
For More Information On This Product,  
Go to: www.freescale.com  
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