Freescale Semiconductor, Inc.
MSCAN Controller
Timer Link
17.9 Timer Link
The msCAN12 generates a timer signal whenever a valid frame has
been received. Because the CAN specification defines a frame to be
valid if no errors occurred before the EOF field has been transmitted
successfully, the timer signal is generated right after the EOF. A pulse of
one bit time is generated. As the msCAN12 receiver engine also
receives the frames being sent by itself, a timer signal is also generated
after a successful transmission.
The previously described timer signal can be routed into the on-chip
timer interface module (ECT). This signal is connected to the Timer n
Channel input under the control of the timer link enable (TLNKEN) bit in
the CMCR0(1).
After timer n has been programmed to capture rising edge events, it can
be used under software control to generate 16-bit time stamps which can
be stored with the received message.
17.10 Clock System
Figure 17-7 shows the structure of the msCAN12 clock generation
circuitry. With this flexible clocking scheme the msCAN12 is able to
handle CAN bus rates ranging from 10 kbps up to 1 Mbps.
CGM
msCAN12
SYSCLK
EXTALi
Time quanta
clock
CGMCANCLK
Prescaler
(1...64)
CLKSRC
CLKSRC
Figure 17-7. Clocking Scheme
1. The timer channel being used for the timer link for CAN0 is channel 4 and for CAN1 is channel
5.
MC68HC912DG128 — Rev 3.0
Technical Data
MSCAN Controller
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