Freescale Semiconductor, Inc.
MSCAN Controller
Table 17-1. msCAN12 Interrupt Vectors
Function
Source
WUPIF
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
OVRIF
RXF
Local Mask
WUPIE
Global Mask
Wake-Up
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
OVRIE
Error
Interrupts
I Bit
Receive
Transmit
RXFIE
TXE0
TXEIE0
TXEIE1
TXEIE2
TXE1
TXE2
17.7 Protocol Violation Protection
The msCAN12 will protect the user from accidentally violating the CAN
protocol through programming errors. The protection logic implements
the following features:
• The receive and transmit error counters cannot be written or
otherwise manipulated.
• All registers which control the configuration of the msCAN12
cannot be modified while the msCAN12 is on-line. The SFTRES
bit in CMCR0 (see msCAN12 Module Control Register 0
(CMCR0)) serves as a lock to protect the following registers:
– msCAN12 module control register 1 (CMCR1)
– msCAN12 bus timing register 0 and 1 (CBTR0, CBTR1)
– msCAN12 identifier acceptance control register (CIDAC)
– msCAN12 identifier acceptance registers (CIDAR0–7)
– msCAN12 identifier mask registers (CIDMR0–7)
• The TxCAN pin is forced to recessive when the msCAN12 is in any
of the low power modes.
Technical Data
MC68HC912DG128 — Rev 3.0
MSCAN Controller
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