Freescale Semiconductor, Inc.
MSCAN Controller
Identifier Acceptance Filter
A filter hit is indicated to the application software by a set RXF (receive
buffer full flag, see msCAN12 Receiver Flag Register (CRFLG)) and
three bits in the identifier acceptance control register (see msCAN12
Identifier Acceptance Control Register (CIDAC)). These identifier hit
flags (IDHIT2–0) clearly identify the filter section that caused the
acceptance. They simplify the application software’s task to identify the
cause of the receiver interrupt. When more than one hit occurs (two or
more filters match) the lower hit has priority.
A very flexible programmable generic identifier acceptance filter has
been introduced in order to reduce the CPU interrupt loading. The filter
is programmable to operate in four different modes:
• Two identifier acceptance filters, each to be applied to:
a) the full 29 bits of the extended identifier and to the following bits
of the CAN frame: RTR, IDE, SRR or
b) the 11 bits of the standard identifier, the RTR and IDE bits of
CAN 2.0A/B messages.
This mode implements two filters for a full length CAN 2.0B
compliant extended identifier. Figure 17-3 shows how the first 32-
bit filter bank (CIDAR0–3, CIDMR0–3) produces a filter 0 hit.
Similarly, the second filter bank (CIDAR4–7, CIDMR4–7)
produces a filter 1 hit.
• Four identifier acceptance filters, each to be applied to:
a) the 14 most significant bits of the extended identifier plus the
SRR and IDE bits of CAN 2.0B messages or
b) the 11 bits of the standard identifier, the RTR and IDE bits of
CAN 2.0A/B messages.
Figure 17-4 shows how the first 32-bit filter bank (CIDAR0–3,
CIDMR0–3) produces filter 0 and 1 hits. Similarly, the second filter
bank (CIDAR4–7, CIDMR4–7) produces filter 2 and 3 hits.
• Eight identifier acceptance filters, each to be applied to the first 8
bits of the identifier. This mode implements eight independent
filters for the first 8 bits of a CAN 2.0A/B compliant standard
identifier or of a CAN 2.0B compliant extended identifier. Figure
17-5 shows how the first 32-bit filter bank (CIDAR0–3, CIDMR0–3)
produces filter 0 to 3 hits. Similarly, the second filter bank
(CIDAR4–7, CIDMR4–7) produces filter 4 to 7 hits.
MC68HC912DG128 — Rev 3.0
Technical Data
MSCAN Controller
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