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68HC912DG128PV8 参数 Datasheet PDF下载

68HC912DG128PV8图片预览
型号: 68HC912DG128PV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
MSCAN Controller  
The msCAN12 will then schedule the message for transmission and will  
signal the successful transmission of the buffer by setting the TXE flag.  
A transmit interrupt will be emitted(1) when TXE is set and this can be  
used to drive the application software to re-load the buffer.  
If more than one buffer is scheduled for transmission when the CAN bus  
becomes available for arbitration, the msCAN12 uses the local priority  
setting of the three buffers for prioritisation. For this purpose every  
transmit buffer has an 8-bit local priority field (PRIO). The application  
software sets this field when the message is set up. The local priority  
reflects the priority of this particular message relative to the set of  
messages being emitted from this node. The lowest binary value of the  
PRIO field is defined to be the highest priority.  
The internal scheduling process takes places whenever the msCAN12  
arbitrates for the bus. This is also the case after the occurrence of a  
transmission error.  
When a high priority message is scheduled by the application software  
it may become necessary to abort a lower priority message being set up  
in one of the three transmit buffers. As messages that are already under  
transmission cannot be aborted, the user has to request the abort by  
setting the corresponding abort request flag (ABTRQ) in the  
transmission control register (CTCR). The msCAN12 grants the request,  
if possible, by setting the corresponding abort request acknowledge  
(ABTAK) and the TXE flag in order to release the buffer and by  
generating a transmit interrupt. The transmit interrupt handler software  
can tell from the setting of the ABTAK flag whether the message was  
aborted (ABTAK=1) or sent in the meantime (ABTAK=0).  
17.5 Identifier Acceptance Filter  
The identifier acceptance registers (CIDAR0–7) define the acceptable  
patterns of the standard or extended identifier (ID10–ID0 or ID28–ID0).  
Any of these bits can be marked don’t care in the identifier mask  
registers (CIDMR0–7).  
1. The transmit interrupt will occur only if not masked. A polling scheme can be applied on TXE  
also.  
Technical Data  
MC68HC912DG128 — Rev 3.0  
MSCAN Controller  
For More Information On This Product,  
Go to: www.freescale.com  
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