Freescale Semiconductor, Inc.
Inter-IC Bus
IIC Programming Examples
MASR
DEC
RXCNT
;DECREASE THE RXCNT
NXMAR
MOVB
RTI
IBDR,RXBUF ;READ DATA AND STORE
15.7.5 Generation of Repeated START
At the end of data transfer, if the master still wants to communicate on
the bus, it can generate another START signal followed by another slave
address without first generating a STOP signal. A program example is
as shown.
RESTART
BSET
MOVB
IBCR,#$04
ANOTHER START (RESTART)
;TRANSMIT THE CALLING ADDRESS
;D0=R/W
CALLING,IBDR
15.7.6 Slave Mode
In the slave interrupt service routine, the module addressed as slave bit
(IAAS) should be tested to check if a calling of its own address has just
been received (see Figure 15-4). If IAAS is set, software should set the
transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the
R/W command bit (SRW). Writing to the IBCR clears the IAAS
automatically. Note that the only time IAAS is read as set is from the
interrupt at the end of the address cycle where an address match
occurred, interrupts resulting from subsequent data transfers will have
IAAS cleared. A data transfer may now be initiated by writing information
to IBDR, for slave transmits, or dummy reading from IBDR, in slave
receive mode. The slave will drive SCL low in-between byte transfers,
SCL is released when the IBDR is accessed in the required mode.
In the slave transmitter routine, the received acknowledge bit (RXAK)
must be tested before transmitting the next byte of data. Setting RXAK
means an ’end of data’ signal from the master receiver, after which it
must be switched from transmitter mode to receiver mode by software.
A dummy read then releases the SCL line so that the master can
generate a STOP signal.
MC68HC912DG128 — Rev 3.0
Technical Data
Inter-IC Bus
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