Freescale Semiconductor, Inc.
Technical Data — MC68HC912DG128
List of Tables
Table
Title
Page
1-1
1-2
2-1
2-2
2-3
3-1
3-2
3-3
3-4
4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
7-1
8-1
8-2
9-1
9-2
Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . .27
Development Tools Ordering Information. . . . . . . . . . . . . . . . .27
M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .32
M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .33
Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . .34
Power and Ground Connection Summary . . . . . . . . . . . . . . . .42
Signal Description Summary . . . . . . . . . . . . . . . . . . . . . . . . . .49
Port Description Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Port Pull-Up, Pull-Down and Reduced Drive Summary . . . . . .60
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Mapping Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Program space Page Index . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Flash Register space Page Index. . . . . . . . . . . . . . . . . . . . . . .86
Test mode program space Page Index. . . . . . . . . . . . . . . . . . .87
RFSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .90
EXSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .91
Effects of ENPE, LAT and ERAS on Array Reads . . . . . . . . .114
2K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . .129
Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Interrupt Vector Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . .144
11-1 Summary of STOP Mode Exit Conditions. . . . . . . . . . . . . . . .172
11-2 Summary of Pseudo STOP Mode Exit Conditions . . . . . . . . .173
11-3 Clock Monitor Time-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
11-4 Real Time Interrupt Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . .186
11-5 COP Watchdog Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
12-1 Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . .196
12-2 PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . .206
MC68HC912DG128 — Rev 3.0
Technical Data
List of Tables
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