Freescale Semiconductor, Inc.
List of Figures
13-5 Block Diagram for Port7 with Output compare / Pulse
Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
13-6 C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .213
14-1 Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .250
14-2 Serial Communications Interface Block Diagram . . . . . . . . . .251
14-3 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . .263
14-4 SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . .264
14-5 SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . . . .265
14-6 Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . .266
15-1 IIC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
15-2 IIC Transmission Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
15-3 IIC Clock Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . .280
15-4 Flow-Chart of Typical IIC Interrupt Routine . . . . . . . . . . . . . .295
16-1 Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . .298
17-1 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17-2 User Model for Message Buffer Organization. . . . . . . . . . . . .316
17-3 32-bit Maskable Identifier Acceptance Filters. . . . . . . . . . . . .320
17-4 16-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . .320
17-5 8-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . .321
17-6 SLEEP Request / Acknowledge Cycle . . . . . . . . . . . . . . . . . .327
17-7 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17-8 Segments within the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . .331
17-9 CAN Standard Compliant Bit Time Segment Settings . . . . . .331
17-10 msCAN12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
17-11 Message Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . .333
17-12 Receive/Transmit Message Buffer Extended Identifier. . . . . .334
17-13 Standard Identifier Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .335
17-14 Identifier Acceptance Registers (1st bank). . . . . . . . . . . . . . .351
17-15 Identifier Acceptance Registers (2nd bank) . . . . . . . . . . . . . .351
17-16 Identifier Mask Registers (1st bank) . . . . . . . . . . . . . . . . . . . .352
17-17 Identifier Mask Registers (2nd bank) . . . . . . . . . . . . . . . . . . .352
18-1 BDM Host to Target Serial Bit Timing. . . . . . . . . . . . . . . . . . .359
18-2 BDM Target to Host Serial Bit Timing (Logic 1) . . . . . . . . . . .359
18-3 BDM Target to Host Serial Bit Timing (Logic 0) . . . . . . . . . . .360
19-1 VFP Conditioning Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
19-2 VFP Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
19-3 Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
19-4 POR and External Reset Timing Diagram . . . . . . . . . . . . . . .396
Technical Data
MC68HC912DG128 — Rev 3.0
List of Figures
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FREESCALE [ Freescale ]
