Freescale Semiconductor, Inc.
Technical Data — MC68HC912DG128
List of Figures
Figure
Title
Page
2-1
3-1
3-2
3-3
3-4
3-5
5-1
5-2
6-1
7-1
7-2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
MC68HC912DG128 Pin Assignments in 112-pin QFP. . . . . . .38
112-pin QFP Mechanical Dimensions (case no987) . . . . . . . .39
PLL Loop FIlter Connections . . . . . . . . . . . . . . . . . . . . . . . . . .41
Common Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . .43
External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . .43
Memory Map after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Memory Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Access Type vsBus Control Pins . . . . . . . . . . . . . . . . . . . . . . .96
Program Sequence Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Erase Sequence Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
10-1 STOP Key Wake-up Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .153
11-1 Internal Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . .157
11-2 PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
11-3 Clock Loss during Normal Operation . . . . . . . . . . . . . . . . . . .162
11-4 No Clock at Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . .164
11-5 STOP Exit and Fast STOP Recovery. . . . . . . . . . . . . . . . . . .167
11-6 Clock Generation Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
11-7 Clock Chain for SCI0, SCI1, RTI, COP. . . . . . . . . . . . . . . . . .181
11-8 Clock Chain for ECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
11-9 Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM. . . . . .183
12-1 Block Diagram of PWM Left-Aligned Output Channel . . . . . .192
12-2 Block Diagram of PWM Center-Aligned Output Channel . . . .193
12-3 PWM Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
13-1 Timer Block Diagram in Latch Mode. . . . . . . . . . . . . . . . . . . .209
13-2 Timer Block Diagram in Queue Mode. . . . . . . . . . . . . . . . . . .210
13-3 8-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . .211
13-4 16-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . .212
MC68HC912DG128 — Rev 3.0
Technical Data
List of Figures
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