Freescale Semiconductor, Inc.
Resets and Interrupts
9.9 Register Stacking
Once enabled, an interrupt request can be recognized at any time after
the I bit in the CCR is cleared. When an interrupt service request is
recognized, the CPU responds at the completion of the instruction being
executed. Interrupt latency varies according to the number of cycles
required to complete the instruction. Some of the longer instructions can
be interrupted and will resume normally after servicing the interrupt.
When the CPU begins to service an interrupt, the instruction queue is
cleared, the return address is calculated, and then it and the contents of
the CPU registers are stacked as shown in Table 9-2.
.
Table 9-2. Stacking Order on Entry to Interrupts
Memory Location
SP – 2
CPU Registers
RTNH : RTNL
YH : YL
XH : XL
SP – 4
SP – 6
SP – 8
SP – 9
B : A
CCR
After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt
service request is pending) is set to prevent other interrupts from
disrupting the interrupt service routine. The interrupt vector for the
highest priority source that was pending at the beginning of the interrupt
sequence is fetched, and execution continues at the referenced location.
At the end of the interrupt service routine, an RTI instruction restores the
content of all registers from information on the stack, and normal
program execution resumes.
If another interrupt is pending at the end of an interrupt service routine,
the register unstacking and restacking is bypassed and the vector of the
interrupt is fetched.
Technical Data
MC68HC912DG128 — Rev 3.0
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
