Freescale Semiconductor, Inc.
Resets and Interrupts
Resets
To prevent a COP reset from being detected during an external reset,
hold the reset pin low for at least 32 cycles. To prevent a or clock monitor
reset from being detected during an external reset, hold the reset pin low
for at least 4096 + 32 cycles. An external RC power-up delay circuit on
the reset pin is not recommended as circuit charge time can cause the
MCU to misinterpret the type of reset that has occurred.
9.7.3 COP Reset
The MCU includes a computer operating properly (COP) system to help
protect against software failures. When COP is enabled, software must
write $55 and $AA (in this order) to the COPRST register in order to keep
a watchdog timer from timing out. Other instructions may be executed
between these writes. A write of any value other than $55 or $AA or
software failing to execute the sequence properly causes a COP reset to
occur. In addition, windowed COP operation can be selected. In this
mode, a write to the COPRST register must occur in the last 25% of the
selected period. A premature write will also reset the part.
9.7.4 Clock Monitor Reset
If clock frequency falls below a predetermined limit when the clock
monitor is enabled, a reset occurs.
MC68HC912DG128 — Rev 3.0
Technical Data
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
