Freescale Semiconductor, Inc.
Technical Data — MC68HC912DG128
Section 10. I/O Ports with Key Wake-up
10.1 Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.3 Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . .148
10.4 Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.2 Introduction
The MC68HC912DG128 offers 16 additional I/O ports with key wake-up
capability.
The key wake-up feature of the MC68HC912DG128 issues an interrupt
that will wake up the CPU when it is in the STOP or WAIT mode. Two
ports are associated with the key wake-up function: port H and port J.
Port H and port J wake-ups are triggered with a rising or falling signal
edge. For each pin which has an interrupt enabled, there is a path to the
interrupt request signal which has no clocked devices when the part is in
stop mode. This allows an active edge to bring the part out of stop.
Digital filtering is included to prevent pulses shorter than a specified
value from waking the part from STOP.
An interrupt is generated when a bit in the KWIFH or KWIFJ register and
its corresponding KWIEH or KWIEJ bit are both set. All 16 bits/pins share
the same interrupt vector. Key wake-ups can be used with the pins
configured as inputs or outputs.
Default register addresses, as established after reset, are indicated in
the following descriptions. For information on re-mapping the register
block, refer to Operating Modes.
MC68HC912DG128 — Rev 3.0
Technical Data
I/O Ports with Key Wake-up
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