Freescale Semiconductor, Inc.
Resets and Interrupts
9.7 Resets
There are four possible sources of reset. Power-on reset (POR), and
external reset on the RESET pin share the normal reset vector. The
computer operating properly (COP) reset and the clock monitor reset
each has a vector. Entry into reset is asynchronous and does not require
a clock but the MCU cannot sequence out of reset without a system
clock.
9.7.1 Power-On Reset
A positive transition on VDD causes a power-on reset (POR). An external
voltage level detector, or other external reset circuits, are the usual
source of reset in a system. The POR circuit only initializes internal
circuitry during cold starts and cannot be used to force a reset as system
voltage drops.
It is important to use an external low voltage reset circuit (for example:
MC34064 or MC33464) to prevent power transitions or corruption of
RAM or EEPROM.
9.7.2 External Reset
The CPU distinguishes between internal and external reset conditions
by sensing whether the reset pin rises to a logic one in less than nine E-
clock cycles after an internal device releases reset. When a reset
condition is sensed, the RESET pin is driven low and a clocked reset
sequence controls when the MCU can begin normal processingby an
internal device for about 16 E-clock cycles, then released. In the case of
a clock monitor error, a 4096 cycle oscillator start-up delay is imposed
before the reset recovery sequence starts (reset is driven low throughout
this 4096 cycle delay). The internal reset recovery sequence then drives
reset low for 16 to 17 cycles and releases the drive to allow reset to rise.
Nine E-clock cycles later the reset pin it is sampled. If the pin is still held
low, the CPU assumes that an external reset has occurred. If the pin is
high, it indicates that the reset was initiated internally by either the COP
system or the clock monitor.
Technical Data
MC68HC912DG128 — Rev 3.0
Resets and Interrupts
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