Freescale Semiconductor, Inc.
Resets and Interrupts
Effects of Reset
If the MCU comes out of reset in an expanded mode, port A and port B
are used for the address/data bus, and port E pins are normally used to
control the external bus (operation of port E pins can be affected by the
PEAR register). Out of reset, port J, port H, port K, port IB, port P, port
S, port T, port CAN[7:4], port AD0 and port AD1 are all configured as
general-purpose inputs.
9.8.5 Central Processing Unit
After reset, the CPU fetches a vector from the appropriate address, then
begins executing instructions. The stack pointer and other CPU registers
are indeterminate immediately after reset. The CCR X and I interrupt
mask bits are set to mask any interrupt requests. The S bit is also set to
inhibit the STOP instruction.
9.8.6 Memory
After reset, the internal register block is located from $0000 to $03FF,
RAM is at $2000 to $3FFF, and EEPROM is located at $0800 to $0FFF.
In single chip mode, one 32-Kbyte Flash module is located from $4000
to $7FFF and $C000 to $FFFF, and the other three 32-Kbyte Flash
modules are accessible through the program page window located from
$8000 to $BFFF. The first 32-Kbyte FLASH EEPROM is also accessible
through the program page window.
9.8.7 Other Resources
The enhanced capture timer (ECT), pulse width modulation timer
(PWM), serial communications interfaces (SCI0 and SCI1), serial
peripheral interface (SPI), inter-IC bus (IIC), Freescale Scalable CAN
modules (FSCAN0 and FSCAN1) and analog-to-digital converters
(ATD0 and ATD1) are off after reset.
MC68HC912DG128 — Rev 3.0
Technical Data
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
