Freescale Semiconductor, Inc.
Resets and Interrupts
Table 9-1. Interrupt Vector Map
CCR
Mask
HPRIO Value to
Elevate
Vector Address
Interrupt Source
Local Enable
$FFDA, $FFDB
$FFD8, $FFD9
Pulse accumulator input edge
SPI serial transfer complete
I bit
PACTL (PAI)
$DA
$D8
I bit
SP0CR1 (SPIE)
SC0CR2
(TIE, TCIE, RIE, ILIE)
$FFD6, $FFD7
$FFD4, $FFD5
SCI 0
SCI 1
I bit
I bit
$D6
$D4
SC1CR2
(TIE, TCIE, RIE, ILIE)
$FFD2, $FFD3
$FFD0, $FFD1
ATD0 or ATD1
I bit
I bit
ATDxCTL2 (ASCIE)
C0RIER (WUPIE)
$D2
$D0
MSCAN 0 wake-up
KWIEJ[7:0] and
KWIEH[7:0]
$FFCE, $FFCF
Key wake-up J or H
I bit
$CE
$FFCC, $FFCD
$FFCA, $FFCB
Modulus down counter underflow
Pulse Accumulator B Overflow
I bit
I bit
MCCTL (MCZI)
PBCTL (PBOVI)
$CC
$CA
C0RIER (RWRNIE,
TWRNIE,
RERRIE, TERRIE,
BOFFIE, OVRIE)
$FFC8, $FFC9
MSCAN 0 errors
I bit
$C8
$FFC6, $FFC7
$FFC4, $FFC5
$FFC2, $FFC3
$FFC0, $FFC1
$FFBE, $FFBF
MSCAN 0 receive
MSCAN 0 transmit
CGM lock and limp home
IIC Bus
I bit
I bit
I bit
I bit
I bit
C0RIER (RXFIE)
C0TCR (TXEIE[2:0])
PLLCR (LOCKIE, LHIE)
IBCR (IBIE)
$C6
$C4
$C2
$C0
$BE
MSCAN 1 wake-up
C1RIER (WUPIE)
C1RIER (RWRNIE,
TWRNIE,
RERRIE, TERRIE,
BOFFIE, OVRIE)
$FFBC, $FFBD
MSCAN 1 errors
I bit
$BC
$FFBA, $FFBB
$FFB8, $FFB9
$FFB6, $FFB7
$FF80–$FFB5
MSCAN 1 receive
MSCAN 1 transmit
Reserved
I bit
I bit
I bit
I bit
C1RIER (RXFIE)
$BA
$B8
C1TCR (TXEIE[2:0])
$B6
Reserved
$80–$B4
Technical Data
MC68HC912DG128 — Rev 3.0
Resets and Interrupts
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