Freescale Semiconductor, Inc.
System Integration Module (SIM)
6.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. (See Figure
6-5.) An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, or POR. (See Figure 6-6.) Note that for LVI
or POR resets, the SIM cycles through 4096 CGMXCLK cycles during
which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 6-5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
IRST
RST PULLED LOW BY MCU
32 CYCLES
RST
32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 6-5. Internal Reset Timing
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
INTERNAL RESET
POR
Figure 6-6. Sources of Internal Reset
Advance Information
86
MC68HC908RFRK2
MOTOROLA
System Integration Module (SIM)
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