Freescale Semiconductor, Inc.
System Integration Module (SIM)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
SBSW
See Note
0
Bit 0
Read:
SIM Break Status Register
R
R
R
R
R
R
R
$FE00
(SBSR) Write:
See page 97.
Reset:
Note: Writing a logic 0 clears SBSW
Read: POR
PIN
COP
ILOP
ILAD
0
LVI
0
SIM Reset Status Register
$FE01
$FE02
(SRSR) Write:
See page 98.
POR:
Read:
1
BCFE
0
X
R
0
X
R
0
X
R
X
R
X
R
0
X
R
0
X
R
0
SIM Break Flag Control
Register (SBFCR) Write:
See page 99.
Reset:
0
0
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 6-2. SIM I/O Register Summary
Table 6-1 shows the internal signal names used in this section.
Table 6-1. Signal Name Conventions
Signal Name
Description
CGMXCLK
Selected clock source from internal clock generator module (ICG)
Clock output from ICG module
Bus clock = CGMOUT divided by two
CGMOUT
ICLK
ECLK
IAB
Output from internal clock generator
External clock source
Internal address bus
IDB
internal data bus
PORRST
IRST
R/W
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Advance Information
82
MC68HC908RFRK2
System Integration Module (SIM)
MOTOROLA
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