Freescale Semiconductor, Inc.
System Integration Module (SIM)
SIM Bus Clock Control and Generation
6.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 6-3. This clock can come
from either an external oscillator or from the internal clock generator
(ICG) module.
6.3.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator
output (ECLK) divided by four or the ICG output (ICLK) divided by four.
6.3.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after 4096 CGMXCLK cycles.
The RST pin is driven low by the SIM during this entire period. The bus
clocks start upon completion of the timeout.
CGMXCLK
SIM COUNTER
ECLK
ICLK
CLOCK
SELECT
CIRCUIT
A
B
CGMOUT
BUS CLOCK
GENERATORS
÷ 2
÷ 2
S*
*When S = 1,
CGMOUT = B
CS
ICG
GENERATOR
SIM
PTB3
MONITOR MODE
USER MODE
ICG
Figure 6-3. ICG Clock Signals
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
83
System Integration Module (SIM)
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
