Freescale Semiconductor, Inc.
System Integration Module (SIM)
6.4.2.2 Computer Operating Properly (COP) Reset
The overflow of the COP counter causes an internal reset and sets the
COP bit in the SIM reset status register (SRSR) if the COPD bit in the
CONFIG register is at logic 0. (See Section 11. Computer Operating
Properly Module (COP).)
6.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the configuration register (CONFIG) is
logic 0, the SIM treats the STOP instruction as an illegal opcode and
causes an illegal opcode reset.
6.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset.
6.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V voltage falls to the V voltage. The LVI bit in the SIM reset
DD
LVR
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG register are at logic 0. The RST pin
will be held low until the SIM counts 4096 CGMXCLK cycles after V
DD
rises above V
+ H
. Another 64 CGMXCLK cycles later, the CPU
LVR
LVR
is released from reset to allow the reset vector sequence to occur. (See
Section 12. Low-Voltage Inhibit (LVI).)
Advance Information
88
MC68HC908RFRK2
System Integration Module (SIM)
MOTOROLA
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