Freescale Semiconductor, Inc.
System Integration Module (SIM)
6.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . .97
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . .98
SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . .99
6.8.1
6.8.2
6.8.3
6.2 Introduction
This section describes the system integration module (SIM). Together
with the central processor unit (CPU), the SIM controls all MCU
activities. The SIM is a system state controller that coordinates CPU and
exception timing. A block diagram of the SIM is shown in Figure 6-1.
Figure 6-2 is a summary of the SIM input/output (I/O) registers.
The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
•
•
Master reset control, including power-on reset (POR) and
computer operating properly (COP) timeout
Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
CPU enable/disable timing
•
Advance Information
80
MC68HC908RFRK2
MOTOROLA
System Integration Module (SIM)
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