Freescale Semiconductor, Inc.
FLASH 2TS Memory
FLASH 2TS Charge Pump Frequency Control
4.5 FLASH 2TS Charge Pump Frequency Control
The internal charge pump, required for program, margin read, and erase
operations, is designed to operate most efficiently with a 2-MHz clock.
The charge pump clock is derived from the bus clock. Table 4-1 shows
how the FDIV bits are used to select a charge pump frequency based on
the bus clock frequency. Program, margin read, and erase operations
cannot be performed if the bus clock frequency is below 2 MHz.
Table 4-1. Charge Pump Clock Frequency
FDIV0
Pump Clock Frequency
Bus frequency ÷ 1
0
1
Bus frequency ÷ 2
NOTE: The charge pump is optimized for 2-MHz operation.
4.6 FLASH 2TS Erase Operation
Use this step-by-step procedure to erase a block of FLASH 2TS
memory. Refer to 17.13 Memory Characteristics for a detailed
description of the times used in this algorithm.
1. Set the ERASE, BLK0, BLK1, and FDIV0 bits in the FLASH 2TS
control register. Refer to Table 4-1 for FDIV settings and to
Table 4-2 for block sizes.
2. Ensure target portion of array is unprotected by reading the block
protect register at address $FFF0. Refer to 4.8 FLASH 2TS Block
Protection and 4.9 FLASH 2TS Block Protect Register for more
information.
3. Write to any FLASH 2TS address with any data within the block
address range desired.
4. Set the HVEN bit.
5. Wait for a time, t
.
Erase
6. Clear the HVEN bit.
MC68HC908RFRK2
MOTOROLA
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FLASH 2TS Memory
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