Freescale Semiconductor, Inc.
FLASH 2TS Memory
FLASH 2TS Control Register
block size is one row of eight bytes. Refer to Table 4-2 for additional
block size options.
NOTE: Sometimes a program disturb condition, in which case an erased bit on
the row being programmed unintentionally becomes programmed,
occurs. The embedded smart programming algorithm implements a
margin read technique to avoid program disturb. The margin read step
of the smart programming algorithm is used to ensure programmed bits
are programmed to sufficient margin for data retention over the device’s
lifetime. In the application code, perform an erase operation after eight
program operations (on the same row) to further avoid program disturb.
For availability of programming tools and more information, contact a
local Motorola representative.
1
NOTE: A security feature prevents viewing of the FLASH 2TS contents.
4.4 FLASH 2TS Control Register
The FLASH 2TS control register (FLCR) controls program, erase, and
margin read operations.
Address: $FE08
Bit 7
0
6
FDIV0
0
5
BLK1
0
4
BLK0
0
3
2
1
Bit 0
PGM
0
Read:
Write:
Reset:
HVEN MARGIN ERASE
0
0
0
0
= Unimplemented
Figure 4-1. FLASH 2TS Control Register (FLCR)
FDIV0 — Frequency Divide Control Bit
This read/write bit selects the factor by which the charge pump clock
is divided from the system clock. See 4.5 FLASH 2TS Charge Pump
Frequency Control.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH 2TS difficult for unauthorized users.
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
FLASH 2TS Memory
45
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