Freescale Semiconductor, Inc.
Memory Map
Input/Output Section
Addr.
Register Name
Bit 7
TRIM7
1
6
5
4
3
TRIM3
0
2
TRIM2
0
1
TRIM1
0
Bit 0
TRIM0
0
Read:
Internal Clock Generator
Trim Register (ICGTR) Write:
TRIM6
TRIM5
TRIM4
$0038
See page 142.
Reset:
0
0
0
Read:
Write:
Reset:
Read:
ICG DCO Divider
Control Register
(ICGDVR)
R
R
0
R
0
R
0
DDIV3
U
DDIV2
U
DDIV1
U
DDIV0
U
$0039
See page 143.
0
ICG DCO Stage Register
DSTG7
DSTG6
DSTG5
DSTG4
DSTG3
DSTG2
DSTG1
DSTG0
$003A
$003B
(ICGDSR) Write:
See page 144.
Reset:
Unaffected by reset
Reserved
Unimplemented
Unimplemented
R
R
R
R
R
R
R
R
$003C
↓
$003F
Read:
SBSW
See Note
0
SIM Break Status Register
R
R
R
R
R
R
0
R
0
$FE00
(SBSR) Write:
See page 97.
Reset:
Note: Writing a logic 0 clears SBSW
Read: POR
PIN
COP
ILOP
ILAD
LVI
SIM Reset Status Register
$FE01
(SRSR) Write:
See page 98.
POR:
Read:
1
X
R
X
R
X
R
X
R
X
R
X
R
X
R
SIM Break Flag Control
BCFE
$FE02
$FE03
Register (SBFCR) Write:
See page 99.
Reset:
0
0
0
0
0
0
0
0
Reserved
R
R
R
R
R
R
R
R
= Unimplemented
R
= Reserved U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 6)
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
37
Memory Map
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
