Freescale Semiconductor, Inc.
Memory Map
Addr.
Register Name
Timer Channel 0 Register
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
$0026
High (TCH0H) Write:
See page 219.
Reset:
Indeterminate after reset
Read:
Timer Channel 0 Register
Bit 7
6
5
0
4
3
2
1
Bit 0
$0027
$0028
$0029
$002A
Low (TCH0L) Write:
See page 219.
Reset:
Indeterminate after reset
Read: CH1F
Timer Channel 1 Status
CH1IE
0
MS1A
0
ELS1B
ELS1A
TOV1 CH1MAX
and Control Register Write:
0
0
(TSC1) See page 215.
Reset:
0
0
0
0
9
0
Read:
Timer Channel 1 Register
Bit 15
14
13
12
11
10
Bit 8
High (TCH1H) Write:
See page 219.
Reset:
Indeterminate after reset
Read:
Timer Channel 1 Register
Bit 7
6
5
4
3
2
1
Bit 0
Low (TCH1L) Write:
See page 219.
Reset:
Indeterminate after reset
$002B
↓
Unimplemented
Unimplemented
$0035
Read:
CMF
ICGS
ECGS
Internal Clock Generator
CMIE
CMON
CS
0
ICGON
ECGON
$0036
$0037
Control Register Write:
(ICGCR) See page 139.
Reset:
0
R
0
0
N6
0
0
N5
0
1
N3
0
0
N2
1
0
N1
0
0
N0
1
Read:
Internal Clock Generator
N4
Multiplier Register Write:
(ICGMR) See page 141.
Reset:
1
= Unimplemented
R
= Reserved U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 6)
Advance Information
36
MC68HC908RFRK2
MOTOROLA
Memory Map
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