Freescale Semiconductor, Inc.
Memory Map
Input/Output Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
FLASH 2TS Block Protect
†
R
R
R
R
BPR3
BPR2
BPR1
BPR0
Register (FLBPR)
$FFF0
See page 52.
Unaffected by reset
† Non-volatile FLASH register
COP Control Register
Read:
Low byte of reset vector
$FFFF
(COPCTL) Write:
See page 167.
Writing clears COP counter (any value)
Unaffected by reset
Reset:
= Unimplemented
R
= Reserved U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 6)
Table 2-1 is a list of vector locations.
Table 2-1. Vector Locations
Address
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
Vector
ICG vector (high)
ICG vector (low)
TIM overflow vector (high)
TIM overflow vector (low)
TIM channel 1 vector (high)
TIM channel 1 vector (low)
TIM channel 0 vector (high)
TIM channel 0 vector (low)
IRQ1/keyboard vector (high)
IRQ1/keyboard vector (low)
SWI vector (high)
SWI vector (low)
Reset vector (high)
Reset vector (low)
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
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Memory Map
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