Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused.
NOTE: In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
15.5.6 Pulse-Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare
channel, the TIM can generate a pulse-width modulation (PWM) signal.
The value in the TIM counter modulo registers determines the period of
the PWM signal. The channel pin toggles when the counter reaches the
value in the TIM counter modulo registers. The time between overflows
is the period of the PWM signal.
As Figure 15-3 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear channel 0 pin on output compare if the state of the PWM
pulse is logic 1. Program the TIM to set the pin if the state of the PWM
pulse is logic 0.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTB2/TCH0
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 15-3. PWM Period and Pulse Width
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MC68HC908RFRK2
MOTOROLA
Timer Interface Module (TIM)
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