Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
Functional Description
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Timer Counter Register
$0022
Low (TCNTL) Write:
See page 213.
Reset:
Read:
0
Bit 15
1
0
0
13
1
0
12
1
0
0
0
9
1
1
1
0
Bit 8
1
Timer Counter Modulo
$0023 Register High (TMODH) Write:
14
11
10
See page 214.
Reset:
1
1
1
Read:
Timer Counter Modulo
Register Low (TMODL) Write:
Bit 7
6
1
5
4
3
2
Bit 0
1
$0024
$0025
$0026
$0027
$0028
$0029
$002A
See page 214.
Reset:
1
1
1
1
ELS0B
0
1
ELS0A
0
Read: CH0F
Timer Channel 0 Status
and Control Register Write:
(TSC0) See page 215.
CH0IE
0
MS0B
0
MS0A
0
TOV0 CH0MAX
0
0
Reset:
0
9
0
Read:
Timer Channel 0 Register
Bit 15
14
13
12
11
10
Bit 8
High (TCH0H) Write:
See page 219.
Reset:
Indeterminate after reset
Read:
Timer Channel 0 Register
Bit 7
6
5
0
4
3
2
1
Bit 0
Low (TCH0L) Write:
See page 219.
Reset:
Indeterminate after reset
Read: CH1F
Timer Channel 1 Status
and Control Register Write:
(TSC1) See page 215.
CH1IE
0
MS1A
0
ELS1B
ELS1A
TOV1 CH1MAX
0
0
Reset:
0
0
0
0
9
0
Read:
Timer Channel 1 Register
Bit 15
14
13
12
11
10
Bit 8
High (TCH1H)) Write:
See page 219.
Reset:
Indeterminate after reset
Read:
Timer Channel 1 Register
Bit 7
6
5
4
3
2
1
Bit 0
Low (TCH1L)) Write:
See page 219.
Reset:
Indeterminate after reset
= Unimplemented
Figure 15-2. TIM I/O Register Summary (Continued)
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
201
Timer Interface Module (TIM)
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