Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
I/O Registers
8.8.1 ICG Control Register
The ICG control register (ICGCR) contains the control and status bits for
the internal clock generator, external clock generator, and clock monitor
as well as the clock select and interrupt enable bits.
Address: $0036
Bit 7
6
5
CMON
0
4
CS
0
3
ICGON
1
2
1
ECGON
0
Bit 0
Read:
Write:
Reset:
CMF
ICGS
ECGS
CMIE
0
0
0
0
= Unimplemented
Figure 8-11. ICG Control Register (ICGCR)
CMIE — Clock Monitor Interrupt Enable Bit
This read/write bit enables clock monitor interrupts. An interrupt will
occur when both CMIE and CMF are set. CMIE can be set when the
CMON bit has been set for at least one cycle. CMIE is forced clear
when CMON is clear or during reset.
1 = Clock monitor interrupts enabled
0 = Clock monitor interrupts disabled
CMF — Clock Monitor Interrupt Flag
This read-only bit is set when the clock monitor determines that either
ICLK or ECLK becomes inactive and the CMON bit is set. This bit is
cleared by first reading the bit while it is set, followed by writing the bit
low. This bit is forced clear when CMON is clear or during reset.
1 = Either ICLK or ECLK has become inactive.
0 = ICLK and ECLK have not become inactive since the last read
of the ICGCR or the clock monitor is disabled.
CMON — Clock Monitor On Bit
This read/write bit enables the clock monitor. CMON can be set when
both ICLK and ECLK have been on and stable for at least one bus
cycle (ICGON, ECGON, ICGS, and ECGS are all set). CMON is
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
Internal Clock Generator Module (ICG)
139
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