Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
I/O Registers
ECGON — External Clock Generator On Bit
This read/write bit enables the external clock generator. ECGON can
be cleared when the CS and CMON bits have been clear for at least
one bus cycle. ECGON is forced set when the CMON bit or the CS bit
is set. ECGON is forced clear during reset.
1 = External clock generator enabled
0 = External clock generator disabled
ECGS — External Clock Generator Stable Bit
This read-only bit indicates when at least 4096 external clock (ECLK)
cycles have elapsed since the external clock generator was enabled.
This is not an assurance of the stability of ECLK but is meant to
provide a startup delay. This bit is forced clear when the clock monitor
determines ECLK is inactive, when ECGON is clear, or during reset.
1 = 4096 ECLK cycles have elapsed since ECGON was set.
0 = External cock is unstable, inactive, or disabled.
8.8.2 ICG Multiplier Register
Address: $0037
Bit 7
6
5
N5
0
4
N4
1
3
N3
0
2
N2
1
1
N1
0
Bit 0
N0
1
Read:
Write:
Reset:
R
N6
0
0
R
= Reserved
Figure 8-12. ICG Multiplier Register (ICGMR)
N6–N0 — ICG Multiplier Factor Bits
These read/write bits change the multiplier used by the internal
clock generator. The internal clock (ICLK) will be
(307.2 kHz ±25 percent) * N. A value of $00 in this register is
interpreted the same as a value of $01. This register cannot be written
when the CMON bit is set. Reset sets this factor to $15 (decimal 21)
for default frequency of 6.45 MHz ±25 percent (1.613 MHz ±25
percent bus).
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
Internal Clock Generator Module (ICG)
141
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