Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
8.7.1 EXTSLOW
Slow external clock (EXTSLOW), when set, will decrease the drive
strength of the oscillator amplifier, enabling low-frequency crystal
operation (30 kHz–100 kHz). When clear, EXTSLOW enables high
frequency crystal operation (1 MHz to 8 MHz).
EXTSLOW, when set, also configures the clock monitor to expect an
external clock source that is slower than the low-frequency base clock
(60 Hz–307.2 kHz). When EXTSLOW is clear, the clock monitor will
expect an external clock faster than the low-frequency base clock
(307.2 kHz–32 MHz).
The default state for this option is clear.
8.8 I/O Registers
The ICG contains five registers, summarized in Figure 8-10. These
registers are:
•
•
•
•
•
ICG control register, ICGCR
ICG multiplier register, ICGMR
ICG trim register, ICGTR
ICG DCO divider control register, ICGDVR
ICG DCO stage control register, ICGDSR
Several of the bits in these registers have interaction where the state of
one bit may force another bit to a particular state or prevent another bit
from being set or cleared. A summary of this interaction is shown in
Table 8-5.
Advance Information
136
MC68HC908RFRK2
Internal Clock Generator Module (ICG)
MOTOROLA
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