Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
I/O Registers
8.8.4 ICG DCO Divider Register
Address: $0039
Bit 7
6
5
R
0
4
R
0
3
DDIV3
U
2
DDIV2
U
1
Bit 0
Read:
R
Write:
R
DDIV1
U
DDIV0
U
Reset:
0
0
R
= Reserved
U = Unaffected
Figure 8-14. ICG DCO Divider Register (ICGDVR)
DDIV3–DDIV0 — ICG DCO Divider Control Bits
These bits indicate the number of divide-by-twos (DDIV) that follow
the digitally controlled oscillator. Incrementing DDIV will add another
divide-by-two, doubling the period (halving the frequency).
Decrementing has the opposite effect. DDIV cannot be written when
ICGON is set to prevent inadvertent frequency shifting. When ICGON
is set, DDIV is controlled by the digital loop filter. The range of valid
values for DDIV is from $0 to $9. Values of $A–$F are interpreted the
same as $9. Since the DCO is active during reset, reset has no effect
on DSTG and the value may vary.
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
Internal Clock Generator Module (ICG)
143
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