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GENERAL RELEASE SPECIFICATION
Table 12-6. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
M oed
H I N Z C
C
O
A
O
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
30 ii
40
50
60 ff
70
5
3
3
6
5
Negate Byte
(Two’s Complement)
— — ↕ ↕ ↕ INH
IX1
IX
No Operation
— — — — — INH
9D
2
NOP
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM AA ii
DIR BA dd
EXT CA hh ll
2
3
4
5
4
3
Logical OR
Accumulator with
Memory
A ← (A) (M)
— — ↕ ↕ —
IX2
IX1
IX
DA ee ff
EA ff
FA
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
39 dd
49
59
69 ff
79
5
3
3
6
5
Rotate Byte Left
through Carry Bit
C
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
36 dd
46
56
66 ff
76
5
3
3
6
5
Rotate Byte Right
through Carry Bit
C
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
RSP
RTI
Reset Stack Pointer
Return from Interrupt
SP ← $00FF
— — — — — INH
9C
80
2
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕ ↕ ↕ ↕ ↕ INH
6
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
INH
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM A2 ii
DIR B2 dd
EXT C2 hh ll
2
3
4
5
4
3
Subtract Memory
Byte and Carry Bit
from Accumulator
A ← (A) – (M) – (C)
— — ↕ ↕ ↕
IX2
IX1
IX
D2 ee ff
E2 ff
F2
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
INH
99
2
2
Set Interrupt Mask
— 1 — — — INH
9B
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
B7 dd
EXT C7 hh ll
4
5
6
5
4
Store Accumulator in
Memory
M ← (A)
— — ↕ ↕ —
IX2
IX1
IX
D7 ee ff
E7 ff
F7
Stop Oscillator and
Enable IRQ Pin
STOP
— 0 — — — INH
8E
2
INSTRUCTION SET
MC68HC805P18
12-12
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