Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Table 12-6. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
M oed
H I N Z C
C
O
A
O
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
Set Bit n
Mn ← 1
— — — — —
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
Branch to
Subroutine
BSR rel
— — — — — REL AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
INH
98
9A
2
2
Clear Interrupt Mask
— 0 — — — INH
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
3F dd
4F
5F
6F ff
7F
5
3
3
6
5
Clear Byte
— — 0 1 — INH
IX1
IX
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM A1 ii
DIR B1 dd
EXT C1 hh ll
2
3
4
5
4
3
Compare
Accumulator with
Memory Byte
(A) – (M)
— — ↕ ↕ ↕
— — ↕ ↕ 1
— — ↕ ↕ 1
IX2
IX1
IX
D1 ee ff
E1 ff
F1
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← ( ) = $FF – (M)
DIR
INH
INH
IX1
IX
33 dd
43
53
63 ff
73
5
3
3
6
5
M
A ← ( ) = $FF – (M)
A
Complement Byte
(One’s Complement)
X ← ( ) = $FF – (M)
X
M ← ( ) = $FF – (M)
M
M ← ( ) = $FF – (M)
M
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM A3 ii
DIR B3 dd
EXT C3 hh ll
2
3
4
5
4
3
Compare Index
Register with
Memory Byte
(X) – (M)
IX2
IX1
IX
D3 ee ff
E3 ff
F3
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
3A dd
4A
5A
6A ff
7A
5
3
3
6
5
Decrement Byte
— — ↕ ↕ — INH
IX1
IX
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM A8 ii
DIR B8 dd
EXT C8 hh ll
2
3
4
5
4
3
EXCLUSIVE OR
Accumulator with
Memory Byte
A ← (A) (M)
— — ↕ ↕ —
IX2
IX1
IX
D8 ee ff
E8 ff
F8
INSTRUCTION SET
MC68HC805P18
12-10
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