Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Table 12-6. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
M oed
H I N Z C
C
O
A
O
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
3C dd
4C
5C
6C ff
7C
5
3
3
6
5
Increment Byte
— — ↕ ↕ — INH
IX1
IX
BC
C
C
D
C
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
IX2
IX1
IX
dd
hh ll
ee ff
ff
2
3
4
3
2
Unconditional Jump
Jump to Subroutine
PC ← Jump Address
— — — — —
EC
FC
BD
C
D
D
D
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
IX2
IX1
IX
dd
hh ll
ee ff
ff
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
— — — — —
ED
FD
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM A6 ii
DIR B6 dd
EXT C6 hh ll
2
3
4
5
4
3
Load Accumulator
with Memory Byte
A ← (M)
— — ↕ ↕ —
IX2
IX1
IX
D6 ee ff
E6 ff
F6
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM AE ii
DIR BE dd
EXT CE hh ll
2
3
4
5
4
3
Load Index Register
with Memory Byte
X ← (M)
— — ↕ ↕ —
IX2
IX1
IX
DE ee ff
EE ff
FE
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
38 dd
48
58
68 ff
78
5
3
3
6
5
Logical Shift Left
(Same as ASL)
C
0
— — ↕ ↕
b7
b0
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
34 dd
44
54
64 ff
74
5
3
3
6
5
0
C
Logical Shift Right
Unsigned Multiply
— — 0 ↕ ↕ INH
b7
b0
IX1
IX
X : A ← (X) × (A)
0 — — — 0
INH
42
11
MUL
INSTRUCTION SET
Rev. 1.0
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