Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Table 12-6. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
M oed
H I N Z C
C
O
A
O
Branch if Half-Carry
Bit Clear
BHCC rel
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
— — — — — REL
— — — — — REL
28 rr
3
Branch if Half-Carry
Bit Set
BHCS rel
BHI rel
29 rr
22 rr
24 rr
3
3
3
Branch if Higher
PC ← (PC) + 2 + rel ? C Z = 0 — — — — — REL
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL
Branch if Higher or
Same
BHS rel
Branch if IRQ Pin
High
BIH rel
BIL rel
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL 2F rr
3
3
Branch if IRQ Pin
Low
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL 2E rr
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM A5 ii
2
3
4
5
4
3
DIR
B5 dd
Bit Test
Accumulator with
Memory Byte
EXT C5 hh ll
(A) (M)
— — ↕ ↕ —
IX2
IX1
IX
D5 ee ff
E5 ff
F5
p
Branch if Lower
(Same as BCS)
BLO rel
BLS rel
PC ← (PC) + 2 + rel ? C = 1
— — — — — REL
25 rr
23 rr
3
3
Branch if Lower or
Same
PC ← (PC) + 2 + rel ? C Z = 1 — — — — — REL
Branch if Interrupt
Mask Clear
BMC rel
BMI rel
BMS rel
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
— — — — — REL 2C rr
— — — — — REL 2B rr
— — — — — REL 2D rr
3
3
3
Branch if Minus
Branch if Interrupt
Mask Set
BNE rel
BPL rel
BRA rel
Branch if Not Equal
Branch if Plus
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — — REL
— — — — — REL 2A rr
— — — — — REL 20 rr
26 rr
3
3
3
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if bit n clear
PC ← (PC) + 2 + rel ? Mn = 0 — — — — ↕
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
PC ← (PC) + 2 + rel ? Mn = 1 — — — — ↕
BRN rel
Branch Never
PC ← (PC) + 2 + rel ? 1 = 0
— — — — — REL
21 rr
3
INSTRUCTION SET
Rev. 1.0
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