Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
12.3.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and
write the modified value back to the memory location or to the register. The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 12-2 lists the
read-modify-write instructions.
Table 12-2. Read-Modify-Write Instructions
Instruction
Mnemonic
ASL
Arithmetic Shift Left
Arithmetic Shift Right
Clear Bit in Memory
Set Bit in Memory
ASR
BCLR
BSET
CLR
Clear
Complement (One’s Complement)
Decrement
COM
DEC
Increment
INC
Logical Shift Left
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
NEG
ROL
ROR
TST
12.3.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is met.
If the test condition is not met, the branch is not performed. All branch instructions
use relative addressing.
Bit test and branch instructions cause a branch based on the state of any readable
bit in the first 256 memory locations. These 3-byte instructions use a combination
of direct addressing and relative addressing. The direct address of the byte to be
tested is in the byte following the opcode. The third byte is the signed offset byte.
The CPU finds the conditional branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its condition
INSTRUCTION SET
Rev. 1.0
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