Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
9.4 A/D Status and Control Register (ADSC)
8
2
The ADSC register reports the completion of A/D conversion and provides control
over oscillator selection, analog subsystem power, and input channel selection.
See Figure 9-1.
3
Bit 7
CC
6
R
0
5
ADON
0
4
0
3
0
2
CH2
0
1
CH1
0
Bit 0
CH0
0
Read:
Write:
Reset:
4
ADSC
$001E
5
0
0
0
= Unimplemented
R
= Reserved
6
Figure 9-1. A/D Status and Control Register
7
CC — Conversion Complete
8
This read-only status bit is set when a conversion sequence has completed and
data is ready to be read from the ADC register. CC is cleared when a channel is
selected for conversion, when data is read from the ADC register, or when the
A/D subsystem is turned off. Once a conversion has been started, conversions
of the selected channel will continue every 32 PH2 clock cycles until the ADSC
register is written to again. During continuous conversion operation, the ADC
register will be updated with new data and the CC bit set every 32 PH2 clock
cycles. Also, data from the previous conversion will be overwritten regardless of
the state of the CC bit.
9
10
11
12
13
14
A
Reserved
This bit is not used currently. It can be read or written, but does not control
anything.
ADON — A/D Subsystem On
When the A/D subsystem is turned on (ADON = 1), it requires a time, t
, to
ADON
stabilize before accurate conversion results can be attained.
16
17
18
19
20
CH2-CH0 — Channel Select Bits
CH2, CH1, and CH0 form a 3-bit field which is used to select an input to the A/D
converter. Channels 0 through 3 correspond to port C input pins PC6 through
PC3. Channels 4 through 6 are used for reference measurements. In user mode
channel 7 is reserved. If a conversion is attempted with channel 7 selected the
result will be $00. Table 9-1 lists the inputs selected by bits CH0 through CH3.
ANALOG-TO-DIGITAL CONVERTER
MC68HC805P18
9-4
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