Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
LEVIRQ — Interrupt request option
8
2
LEVIRQ may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = The IRQ pin is edge-sensitive (erased state).
1 = The IRQ pin is edge- and level-sensitive.
3
LSBF — SIOP MSB or LSB first
LSBF may be read at any time. In user mode, writing has no effect. It has to be
programmed in bootloader mode.
4
0 = The SIOP sends/receives MSB (bit 7) first (erased state).
1 = The SIOP sends/receives LSB (bit 0) first.
5
SPR1 and SPR0 — SIOP Rate Select Bits
6
These bits may be read at any time. In user mode, writing has no effect. It has
to be programmed in bootloader mode.
7
8
Table 8-2. SIOP Clock Rate Selection
SPR1
SPR0
Frequency
fOSC divided by 16
9
0
0
1
1
0
1
0
1
fOSC divided by 8
fOSC divided by 4
fOSC divided by 2
10
11
12
13
14
A
SWAIT — STOP conversion to WAIT
SWAIT may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = STOP instruction puts MCU in stop mode.
1 = STOP instruction puts MCU in halt mode.
LVRE — LVR enable/disable
LVRE may be read at any time. In user mode, writing has no effect. It has to be
programmed in bootloader mode.
16
17
18
19
20
0 = The LVR is disabled (erased state).
1 = The LVR is enabled.
CLKOUT — CLKOUT enable/disable
CLKOUT may be read at any time. In user mode, writing has no effect. It has to
be programmed in bootloader mode.
0 = The CLKOUT is disabled (erased state).
1 = The CLKOUT is enabled.
EEPROM
Rev. 1.0
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