GENERAL RELEASE SPECIFICATION
August 27, 1998
CDIF — Current Detect Interrupt Flag
This read-only bit is set when the voltage developed across the sense resistor,
R
is equal to or greater than V
(the CSA comparator trip voltage,
SENSE
DET
typically –15mV) CDIF generates an interrupt request to the CPU if CDIE is
also set. The CDIF bit is cleared by writing a logic “1” to the CDIFR bit. Writing
to CDIF has no effect. Reset clears CDIF.
1 = Current detect interrupt has occurred.
0 = No current detect interrupt since CDIF last cleared.
If the OSC1 and OSC2 pins are not enabled (by mask option). The current detect
interrupt from CDIF bit can be reflected to one of two output port pins, PB2/CS0
and PB3/CS1.
BIT 7
TSEN
0
BIT 6
LVRON
1
BIT 5
BIT 4
SCLK
0
BIT 3
CSSEL
0
BIT 2
TCSEL
0
BIT 1
BIT 0
MCR
R
0
COPON
0
ESVEN SMINLEV
$000B
W
reset:
0
0
U = UNAFFECTED BY RESET
Figure 13-3. Miscellaneous Control Register (MCR)
CSSEL — Current Sense detect output Select
This read/write bit selects either CS0 pin or CS1 pin is used to reflect the cur-
rent detect interrupt. Reset clears the CSSEL bit.
1 = CS1 enabled, CS0 disabled.
0 = CS0 enabled, CS1 disabled.
Table 13-3. Current Detect Output Select
CDEN
CSSEL
PB2/CS0
PB2
PB3/CS1
PB3
0
0
1
1
0
1
0
1
PB2
PB3
CS0
PB3
PB2
CS1
CS0 and CS1 are not available when OSC1 and OSC2 are used for external oscil-
lator option.
13.4 CSA OPERATION DURING WAIT MODE
In WAIT mode the CSA module continues to operate and may generate an inter-
rupt to trigger the MCU out of WAIT mode.
13.5 CSA OPERATION DURING STOP MODE
In STOP mode the CSA module is disabled; but a CSA interrupt (by CDIF) can
wake-up the MCU from the STOP mode.
MOTOROLA
13-4
CURRENT SENSE AMPLIFIER
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
