GENERAL RELEASE SPECIFICATION
August 27, 1998
PB1
TCAP
2 TO 1
MUX
2 TO 1
MUX
TCAP
V
DD
SCL
I
TCSEL
BIT 2 OF MCR ($0B)
CHG
CHG
CHARGE
CURRENT
CONTROL
LOGIC
CAP
ATD1
I
ATD2
ISEN
DISCHG
CPEN
ICEN
CPIE
+
COMP
–
V
DD
INV
CPF
PORTB
LOGIC
MUX0
MUX1
MUX2
CMP
PB7
AN0
SAMPLE
CAP
PORTB
LOGIC
PB6
AN1
PORTB
LOGIC
ANALOG
INTERRUPT
PB5
AN2
HOLD
PORTB
LOGIC
MUX3
MUX4
DHOLD
PB4
AN3
INV
VREF
MUX3
MUX2
MUX1
MUX0
VREF
AN4
TM
CSA
VM
MUX7
MUX6
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
IBREF
(see Figure 13-1)
CURRENT
SENSE
AMPLIFIER
CIRCUIT
MUX6
AN6
MUX7
AN7
V
IBREF
AOFF
MUX5
AN5
MUX7
MUX6
MUX5
MUX4
+
–
V
INTERNAL
TEMPERATURE
SENSOR
SS
TSEN
BIT 7 OF MCR ($0B)
IBREF
INTERNAL
BANDGAP
REFERENCE
V
IB
DENOTES
INTERNAL
CHIP AV
SS
Figure 15-1. Analog Subsystem Block Diagram
MOTOROLA
15-2
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
